1. Field of the Invention
The present invention relates to a read-only memory (ROM) storing information by using a pair of memory cells.
2. Description of the Related Art
Conventionally, a mask ROM is programmed by using a diffusion method, contact method, via contact method, or the like as disclosed in, e.g., Jpn. Pat. Appln. KOKAI Publication No. H11-26607.
The diffusion method programs binary data in accordance with whether to form source and/or drain regions of a transistor which functions as a memory cell. When a transistor having source and drain regions is selected, this transistor is turned on to change the potential of a precharged bit line. If source and drain regions are not formed, a transistor does not function as a switch, so a bit line maintains a precharged state. Data is read by making the potential of the bit line correspond to “1” or “0” of data.
On the other hand, the contact method or via contact method programs binary data in accordance with the presence/absence of a contact or via contact of a transistor in a memory cell. Whether to transfer memory cell data to a bit line is determined in accordance with the presence/absence of the contact or via contact, and the potential of a precharged bit line changes in accordance with the presence/absence of these contacts. Data is read by making this potential change of the bit line correspond to “1” or “0” of data.
In any of the conventional mask ROMs described above, however, data is programmed by using a mask during the fabrication process, so the data cannot be rewritten after the fabrication. Also, the mask ROM cannot be given the function of a monitor tool for detecting variations in the element formation process or inconveniences after the device is fabricated.
Note that the above-mentioned mask ROM is a nonvolatile storage circuit which stores one-bit information at one address. However, Jpn. Pat. Appln. KOKAI Publication No. P2003-203994, for example, has disclosed a technique which determines binary data by using the result of comparison of the electrical characteristics of a pair of a PMOS transistor and NMOS transistor.